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ISL22323 Dual Digitally Controlled Potentiometer (XDCPTM)
Data Sheet March 13, 2008 FN6422.1
Low Noise, Low Power, I2C(R) Bus, 256 Taps
The ISL22323 integrates two digitally controlled potentiometers (DCP), control logic and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WRi) and a non-volatile Initial Value Register (IVRi) that can be directly written to and read by the user. The contents of the WRi control the position of the corresponding wiper. At power up the device recalls the contents of the DCP's IVRi to the correspondent WRi. The ISL22323 also has 13 general purpose non-volatile registers that can be used as storage of lookup table for multiple wiper position or any other valuable information. The ISL22323 features a dual supply, that is beneficial for applications requiring a bipolar range for DCP terminals between V- and VCC. Each DCP can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* Two potentiometers in one package * 256 resistor taps * I2C serial interface - Three address pins, up to eight devices per bus * Non-volatile EEPROM storage of wiper position * 13 General Purpose non-volatile registers * High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T +55C * Wiper resistance: 70 typical @ 1mA * Standby current <4A max * Shut-down current <4A max * Dual power supply - VCC = 2.25V to 5.5V - V- = -2.25V to -5.5V * 10k, 50k or 100k total resistance * Extended industrial temperature range: -40 to +125C * 14 Ld TSSOP or 16 Ld QFN * Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Notes 1, 2) ISL22323TFV14Z ISL22323TFR16Z ISL22323UFV14Z ISL22323UFR16Z ISL22323WFV14Z ISL22323WFR16Z NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. PART MARKING 22323 TFVZ 223 23TFRZ 22323 UFVZ 223 23UFRZ 22323 WFVZ 223 23WFRZ RESISTANCE OPTION (k) 100 100 50 50 10 10 TEMPERATURE RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 14 Ld TSSOP 16 Ld QFN 14 Ld TSSOP 16 Ld QFN 14 Ld TSSOP 16 Ld QFN PKG. DWG. # M14.173 L16.4x4A M14.173 L16.4x4A M14.173 L16.4x4A
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL22323 Block Diagram
VCC VRH0 RH1
SCL SDA A2 A1 A0 I2C INTERFACE
POWER UP INTERFACE, CONTROL AND STATUS LOGIC
WR0 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY
WR1 VOLATILE REGISTER AND WIPER CONTROL CIRCUITRY
NON-VOLATILE REGISTERS
GND
RW0
RL0
RW1
RL1
Pinouts
ISL22323 (14 LD TSSOP) TOP VIEW
RW1 RH0 RL0 RW0 RH1 RL1 RW1 A2 1 2 3 4 5 6 7 14 VCC 13 A0 12 A1 11 GND 10 SCL 9 8 SDA VA2 NC NC V1 2 3 4 5 SDA 6 SCL 7 GND 8 A1
ISL22323 (16 LD QFN) TOP VIEW
RW0 13 12 RL0 11 RH0 10 VCC 9 A0 RH1 14 RL1 15
16
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FN6422.1 March 13, 2008
ISL22323 Pin Descriptions
TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 QFN PIN 11 12 13 14 15 16 1 4 5 6 7 8 9 10 2, 3 EPAD* SYMBOL RH0 RL0 RW0 RH1 RL1 RW1 A2 VSDA SCL GND A1 A0 VCC NC "High" terminal of DCP0 "Low" terminal of DCP0 "Wiper" terminal of DCP0 "High" terminal of DCP1 "Low" terminal of DCP1 "Wiper" terminal of DCP1 Device address input for the I2C interface Negative power supply pin Open drain Serial data I/O for the I2C interface I2C interface clock input Device ground pin Device address input for the I2C interface Device address input for the I2C interface Positive power supply pin No connection Exposed Die Pad internally connected to VDESCRIPTION
NOTE: *PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf
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FN6422.1 March 13, 2008
ISL22323
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V Voltage at any DCP Pin with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A at +125C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) JC (C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . 105 N/A 16 Lead QFN (Note 4) . . . . . . . . . . . . . 39 3.0 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Full Industrial) . . . . . . . . . . . .-40C to +125C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.25V to -5.5V Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option T option MIN (Note 21) TYP (Note 5) 10 50 100 -20 W option U, T option 85 45 V70 10/10/25 0.1 1 VCC 250 +20 MAX (Note 21) UNIT k k k % ppm/C ppm/C V pF A
PARAMETER RHi to RLi Resistance
RHi to RLi Resistance Tolerance End-to-End Temperature Coefficient
VRHi, VRLi RW CH/CL/CW (Note 19) ILkgDCP
DCP Terminal Voltage Wiper Resistance Potentiometer Capacitance Leakage on DCP Pins
VRH and VRL to GND RH - floating, VRL = V-, force Iw current to the wiper, IW = (VCC - VRL)/RTOTAL See Macro Model below. Voltage at pin from V- to VCC
VOLTAGE DIVIDER MODE (V- @ RLi; VCC @ RHi; measured at RWi, unloaded) INL (Note 10) Integral Non-linearity Monotonic Over All Tap Positions W option U, T option DNL (Note 9) Differential Non-linearity Monotonic Over All Tap Positions W option U, T option ZSerror (Note 7) FSerror (Note 8) VMATCH (Note 11, 19) Zero-scale Error W option U, T option Full-scale Error W option U, T option DCP-to-DCP Matching Wipers at the same tap position, the same voltage at all RH terminals and the same voltage at all RL terminals -1.5 -1.0 -1.0 -0.5 0 0 -5 -2 -2 0.5 0.2 0.4 0.15 1 0.5 -1 -1 1.5 1.0 1.0 0.5 5 2 0 0 2 LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6) LSB (Note 6)
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FN6422.1 March 13, 2008
ISL22323
Analog Specifications
SYMBOL Over recommended operating conditions unless otherwise stated. (Continued) TEST CONDITIONS DCP register set to 80 hex Wiper at midpoint (80hex) W option (10k) Wiper at midpoint (80hex) U option (50k) Wiper at midpoint (80hex) T option (100k) MIN (Note 21) TYP (Note 5) 4 1000 250 120 MAX (Note 21) UNIT ppm/C kHz kHz kHz
PARAMETER
TCV (Note 12, Ratiometric Temperature Coefficient 19) fcutoff (Note 19) -3dB Cut Off Frequency
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected) RINL (Note 16) Integral Non-linearity W option U, T option RDNL (Note 15) Differential Non-linearity W option U, T option Roffset (Note 14) Offset W option U, T option RMATCH (Note 17) DCP-to-DCP Matching Wipers at the same tap position with the same terminal voltages DCP register set between 32hex and FF hex -3 -1 -1.5 -0.5 0 0 -2 40 1.5 0.4 0.5 0.15 1 0.5 3 1 1.5 0.5 5 2 2 MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) MI (Note 13) ppm/C
TCR Resistance Temperature Coefficient (Notes 18, 19)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 PARAMETER VCC Supply Current (Volatile Write/Read) TEST CONDITIONS VCC = 5.5V, fSCL = 400kHz; (for I2C Active, Read and Volatile Write states only) VCC = 2.25V, fSCL = 400kHz; (for I2C Active, Read and Volatile Write states only) IV-1 V- Supply Current (Volatile Write/Read) V- = -5.5V, VCC = 5.5V, fSCL = 400kHz; (for I2C Active, Read and Volatile Write states only) V- = -2.25V, VCC = 2.25V, fSCL = 400kHz; (for I2C Active, Read and Volatile Write states only) ICC2 VCC Supply Current (Non-volatile Write/Read) VCC = 5.5V, V- = 5.5V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) VCC = 2.25V, V- = -2.25V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) IV-2 V- Supply Current (Non-volatile Write/Read) V- Supply Current (Non-volatile Write/Read) V- = -5.5V, VCC = 5.5V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) V- = -2.25V, VCC = 2.25V, fSCL = 400kHz; (for I2C Active, Read and Non-volatile Write states only) -2.0 -0.2 0.005 -0.05 0.1 mA mA MIN (Note 21) TYP (Note 5) 0.01 MAX (Note 21) 0.2 UNIT mA
-0.1
-0.02
mA
1.0
2.0
mA
0.3
1.0
mA
-1.2
mA
-1.0
-0.4
mA
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FN6422.1 March 13, 2008
ISL22323
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL ISB PARAMETER VCC Current (Standby) TEST CONDITIONS VCC = +5.5V, V- = -5.5V @ +85C, I2C interface in standby state VCC = +5.5V, V- = -5.5V @ +125C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +85C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +125C, I2C interface in standby state IV-SB V- Current (Standby) V- = -5.5V, VCC = +5.5V @ +85C, I2C interface in standby state V- = -5.5V, VCC = +5.5V @ +125C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +85C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +125C, I2C interface in standby state ISD VCC Current (Shut-down) VCC = +5.5V, V- = -5.5V @ +85C, I2C interface in standby state VCC = +5.5V, V- = -5.5V @ +125C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +85C, I2C interface in standby state VCC = +2.25V, V- = -2.25V @ +125C, I2C interface in standby state IV-SB V- Current (Standby) V- = -5.5V, VCC = +5.5V @ +85C, I2C interface in standby state V- = -5.5V, VCC = +5.5V @ +125C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +85C, I2C interface in standby state V- = -2.25V, VCC = +2.25V @ +125C, I2C interface in standby state ILkgDig tWRT (Note 19) tShdnRec (Note 19) Vpor VCCRamp tD Leakage Current, at Pins A0, A1, A2, SDA, and SCL DCP Wiper Response Time DCP Recall Time from Shut-down Mode Power-on Recall Voltage VCC Ramp Rate Power-up Delay VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state Voltage at pin from GND to VCC SCL falling edge of last bit of DCP data byte to wiper new position SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection Minimum VCC at which memory recall occurs 1.9 0.2 5 -3.0 -5.0 -2.0 -3.0 -1 1.5 1.5 2.1 -3.0 -5.0 -2.0 -3.0 1.0 0.2 0.5 -0.7 -1.5 -0.3 -0.4 0.5 1.0 0.2 0.5 -0.7 -1.5 -0.3 -0.4 1 2.0 4.0 1.0 2.0 4.0 1.0 2.0 A A A A A A A A A A A A A A A A s s V V/ms ms MIN (Note 21) TYP (Note 5) 0.5 MAX (Note 21) 2.0 UNIT A
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FN6422.1 March 13, 2008
ISL22323
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL PARAMETER TEST CONDITIONS MIN (Note 21) TYP (Note 5) MAX (Note 21) UNIT
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 20) Non-volatile Write Cycle Time Temperature T +55C 1,000,000 50 12 20 Cycles Years ms
SERIAL INTERFACE SPECS VIL VIH Hysteresis (Note 19) VOL (Note 19) Cpin (Note 19) fSCL tsp tAA (Note 19) tBUF (Note 19) tLOW tHIGH tSU:STA tHD:STA tSU:DAT A0, A1, A2, SDA, and SCL Input Buffer LOW Voltage A0, A1, A2, SDA, and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 4mA A0, A1, A2, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is and SCL Inputs suppressed SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window Valid Time the Bus Must be Free Before The SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge; both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge; both crossing 70% of VCC From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window From 30% to 70% of VCC From 70% to 30% of VCC 1300 0.7*VCC 0.05*VCC 0 0.4 10 400 50 900 0.3*VCC V V V V pF kHz ns ns ns
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT
Input Data Hold Time
0
ns
tSU:STO tHD:STO tDH (Note 19) tR (Note 19) tF (Note 19)
STOP Condition Setup Time STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time
600 1300 0
ns ns ns
SDA and SCL Rise Time SDA and SCL Fall Time
20 + 0.1*Cb 20 + 0.1*Cb
250 250
ns ns
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FN6422.1 March 13, 2008
ISL22323
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL Cb (Note 19) Rpu (Note 19) tSU:A tHD:A NOTES: 5. Typical values are for TA = +25C and 3.3V supply voltage. 6. LSB: [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)255 - VCC]/LSB. 9. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 10. INL = [V(RW)i - i * LSB - V(RW)0]/LSB for i = 1 to 255 11. VMATCH= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 1, y = 0 to 1. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 12. TC = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 240 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 +165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 13. MI = |RW255 - RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 14. ROFFSET = RW0/MI, when measuring between RW and RL. ROFFSET = RW255/MI, when measuring between RW and RH. 15. RDNL = (RWi - RWi-1)/MI -1, for i = 16 to 255. 16. RINL = [RWi - (MI * i) - RW0]/MI, for i = 16 to 255. 17. RMATCH= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 1, y = 0 to 1. 18.
6 for i = 16 to 240, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min ( ) is [ Max ( Ri ) - Min ( Ri ) ] 10 TC R = --------------------------------------------------------------- x ---------------- the minimum value of the resistance over the temperature range. [ Max ( Ri ) + Min ( Ri ) ] 2 +165C 19. This parameter is not 100% tested.
PARAMETER Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip A0, A1, and A2 Setup Time A0, A1, and A2 Hold Time
TEST CONDITIONS Total on-chip and off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k ~ 2.5k For Cb = 40pF, max is about 15k ~ 20k Before START condition After STOP condition
MIN (Note 21) 10 1
TYP (Note 5)
MAX (Note 21) 400
UNIT pF k
600 600
ns ns
20. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. 21. Parts are 100% tested at +25C. Temperature limits established by characterization and are not production tested.
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FN6422.1 March 13, 2008
ISL22323
DCP Macro Model
RTOTAL RH CH CL CW 10pF RL
10pF RW
25pF
SDA vs SCL Timing
tF tHIGH tLOW tR tsp
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
A0, A1 and A2 Pin Timing
START SCL CLK 1 STOP
SDA tSU:A A0, A1, A2 tHD:A
Typical Performance Curves
80 T = +125C 70 WIPER RESISTANCE () STANDBY CURRENT (A) 60 T = +25C 50 40 30 20 10 0 0 50 100 150 200 250 TAP POSITION (DECIMAL) T = -40C 1.5 1.0 0.5 0 -0.5 IV-1.0 -1.5 -2.0 -40 ICC 2.0
0
40 TEMPERATURE (C)
80
120
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10k (W)
FIGURE 2. STANDBY ICC and IV- vs TEMPERATURE
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FN6422.1 March 13, 2008
ISL22323 Typical Performance Curves
0.50 T = +25C VCC = 2.25V 0.25 DNL (LSB) 0.25
(Continued)
0.50 VCC = 5.5V T = +25C
INL (LSB) VCC = 5.5V
0
0
-0.25
-0.25
VCC = 2.25V -0.50 200 250 0 50 100 150 200 250
-0.50 0 50 100 150 TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
2.0 10k 1.6 FS ERROR (LSB)
0
-1
VCC = 2.25V 50k VCC = 5.5V
ZS ERROR (LSB)
1.2
-2
0.8 VCC = 2.25V 0.4
50k VCC = 5.5V
-3
10k
-4
0 -40
0
40 TEMPERATURE (C)
80
120
-5
-40
0
40 TEMPERATURE (C)
80
120
FIGURE 5. ZS ERROR vs TEMPERATURE
FIGURE 6. FS ERROR vs TEMPERATURE
0.5 T = +25C 0.25 RDNL (MI) VCC = 5.5V
2.0 T = +25C 1.5 VCC = 2.25V
1.0 0 RINL (MI) VCC = 2.25V -0.50 0 50 100 150 200 250 TAP POSITION (DECIMAL) -0.5 0
0.5
-0.25 0 VCC = 5.5V 50 100 150 200 250
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
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FN6422.1 March 13, 2008
ISL22323 Typical Performance Curves
1.60 10k 1.20 RTOTAL CHANGE (%) 160 10k TCv (ppm/C) 0.80 120 5.5V
(Continued)
200
0.40
80
0.00 2.25V -0.40 -40 0 40 TEMPERATURE (C) 80 50k
40
50k
0 120
16
66
116
166
216
266
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
500 INPUT 400 10k OUTPUT
TCr (ppm/C)
300
200 50k 100 WIPER AT MID POINT (POSITION 80h) RTOTAL = 10k 16 66 116 166 216 TAP POSITION (DECIMAL)
0
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 12. FREQUENCY RESPONSE (1MHz)
CS SCL
WIPER UNLOADED, WIPER MOVEMENT FROM 0h to FFh
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
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FN6422.1 March 13, 2008
ISL22323 Pin Description
Potentiometers Pins
RHI AND RLi The high (RHi) and low (RLi) terminals of the ISL22323 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 255 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. RWi RWi is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. loaded into the corresponding WRi to set the wipers to their initial positions.
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi pins). The RWi pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WRi). When the WRi of a DCP contains all zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is closest to its "Low" terminal (RLi). When the WRi register of a DCP contains all ones (WRi[7:0] = FFh), its wiper terminal (RWi) is closest to its "High" terminal (RHi). As the value of the WRi increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RLi to the position closest to RHi. At the same time, the resistance between RWi and RLi increases monotonically, while the resistance between RHi and RWi decreases monotonically. While the ISL22323 is being powered up, the WRi is reset to 80h (128 decimal), which locates RWi roughly at the center between RLi and RHi. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WRi will be reloaded with the value stored in corresponding non-volatile Initial Value Register (IVRi). The WRi and IVRi can be read or written to directly using the I2C serial interface as described in the following sections.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor. DEVICE ADDRESS (A2, A1, A0) The address inputs are used to set the least significant 3 bits of the 7-bit I2C interface slave address. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the ISL22323. A maximum of eight ISL22323 devices may occupy the I2C serial bus (See Table 3).
Memory Description
The ISL22323 contains two non-volatile 8-bit Initial Value Register (IVRi), thirteen General Purpose non-volatile 8-bit registers and three volatile 8-bit registers: two Wiper Registers (WRi) and Access Control Register (ACR). Memory map of ISL22323 is in Table 1. The non-volatile registers (IVRi) at address 0 and 1, contain initial wiper position and volatile registers (WRi) contain current wiper position.
TABLE 1. MEMORY MAP ADDRESS (hex) 10 F E D C B A 9 8 General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose NON-VOLATILE N/A Reserved N/A N/A N/A N/A N/A N/A N/A VOLATILE ACR
Principles of Operation
The ISL22323 is an integrated circuit incorporating two DCPs with its associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor arrays are comprised of individual resistors connected in a series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi are recalled and
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ISL22323
TABLE 1. MEMORY MAP (Continued) ADDRESS (hex) 7 6 5 4 3 2 1 0 NON-VOLATILE General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose IVR1 IVR0 VOLATILE N/A N/A N/A N/A N/A N/A WR1 WR0
transmit and receive operations. Therefore, the ISL22323 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 16). On power-up of the ISL22323, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22323 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 16). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 16). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK (Acknowledge) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 17). The ISL22323 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22323 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 1010 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is "1" for a Read operation and "0" for a Write operation (See Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
LOGIC VALUES AT PINS A2, A1 AND A0, RESPECTIVELY
The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit (ACR[7]) determines whether the access to wiper registers WRi or initial value registers IVRi.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # NAME 7 VOL 6 SHDN 5 WIP
4 0
3 0
2 0
1 0
0 0
If VOL bit is 0, the non-volatile IVRi registers are accessible. If VOL bit is 1, only the volatile WRi are accessible. Note: value is written to IVRi register also is written to the corresponding WRi. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shut-down mode. When this bit is 0, DCPs are in Shut-down mode. Default value of the SHDN bit is 1.
RHi
RWi
RLi
FIGURE 15. DCP CONNECTION IN SHUT-DOWN MODE
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WRi or ACR while WIP bit is 1.
I2C Serial Interface
The ISL22323 supports an I2C bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both
1 (MSB)
0
1
0
A2
A1
A0
R/W (LSB)
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ISL22323
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 16. VALID DATA CHANGES, START AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM THE MASTER
S T A R T
WRITE IDENTIFICATION BYTE ADDRESS BYTE DATA BYTE S T O P
SIGNAL AT SDA SIGNALS FROM THE SLAVE
1 0 1 0 A2 A1 A0 0 A C K
0000 A C K A C K
FIGURE 18. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W = 0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W = 1
A C K
A C K
S AT CO KP
SIGNAL AT SDA
1 0 1 0 A2 A1 A0 0 A C K
0000 A C K
1 0 1 0 A2 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 19. READ SEQUENCE
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ISL22323
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22323 responds with an ACK. At this time, the device enters its standby state (See Figure 18). The non-volatile write cycle starts after STOP condition is determined and it requires up to 20ms delay for the next non-volatile write. Thus, non-volatile registers must be written individually.
Applications Information
Wiper Transition
When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients (or overshoot/undershoot) resulting from the sudden transition from a very low impedance "make" to a much higher impedance "break within an extremely short period of time (<50ns). Two such code transitions are EFh to F0h, and 0Fh to 10h. Note that all switching transients will settle well within the settling time as stated on the datasheet. A small capacitor can be added externally to reduce the amplitude of these voltage transients, but that will also reduce the useful bandwidth of the circuit, thus this may not be a good solution for some applications. It may be a good idea, in that case, to use fast amplifiers in a signal chain for fast recovery.
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 19). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL22323 responds with an ACK. Then the ISL22323 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The Data Bytes are from the registers indicated by an internal pointer. This pointers initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 0Fh, the pointer "rolls over" to 00h, and the device continues to output data for each ACK received.The master terminates the read operation issuing a NACK (ACK) and a STOP condition following the last bit of the last Data Byte (See Figure 19).
Application Example
Figure 20 shows an example of using ISL22323 for gain setting and offset correction in high side current measurement application. DCP0 applies a programmable offset voltage of 25mV to the FB+ pin of the Instrumentation Amplifier EL8173 to adjust output offset to zero voltages. DCP1 programs the gain of the EL8173 from 90 to 110 with 5V output for 10A current through current sense resistor. More application examples can be found at: http://www.intersil.com/data/an/AN1145.pdf
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ISL22323
1.2V DC/DC CONVERTER OUTPUT PROCESSOR LOAD 10A, MAX
0.005
10k
0.1F
10k
+5V 8 VS+ 3 IN+ EN EL8173IS
1
2 INVOUT 7 FB+ +5V R1 50k, 1% RH0 RW0 50k RL0 DCP0 (1/2 ISL22323U) PROGRAMMABLE OFFSET 25mV R3 50k, 1% -5V ISL22323UFV14Z +5V I2C BUS 14 10 9 7 12 13 11 -5V 8 VCC SCL SDA A2 A1 A0 GND VRH0 RL0 RW0 RH1 RL1 RW1 1 2 3 4 5 6 DCP0 R2 1k, 1% RW1 50k RL1 5 FB- V S 4 RH1 R5 309, 1% R4 150k, 1% 6 VOUT = 0V TO +5V to ADC
DCP1 (1/2 ISL22323U) PROGRAMMABLE GAIN 90 TO 110 R6 1.37k, 1%
DCP1
FIGURE 20. CURRENT SENSING WITH GAIN AND OFFSET CONTROL
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FN6422.1 March 13, 2008
ISL22323 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGD-10) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.30 2.30 2.30 0.18 MIN 0.80 NOMINAL 0.90 0.20 REF 0.25 4.00 BSC 3.75 BSC 2.40 4.00 BSC 3.75 BSC 2.40 0.50 BSC 0.40 16 4 4 0.60 12 0.50 0.15 2.55 2.55 0.30 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 2 3/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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FN6422.1 March 13, 2008
ISL22323 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06
e
b 0.10(0.004) M C AM BS
A1 0.10(0.004)
A2 c
D E1 e E L N
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN6422.1 March 13, 2008

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